1. Field of the Invention
The present invention relates to a crosspoint structure semiconductor memory device including a plurality of upper electrode interconnectings extending in the same direction and a plurality of lower electrode interconnectings extending in a direction orthogonal to the extension direction of the upper electrode interconnectings, and having a storage material member for storing data formed between the upper electrode interconnectings and the lower electrode interconnectings, and to a manufacturing method thereof.
2. Description of the Related Art
Generally, in a semiconductor memory device such as a dynamic random access memory (DRAM), a NOR flash memory, or an ferroelectric random access memory (FeRAM), one memory cell is configured by a memory element section that stores data and a selection transistor that selects one memory element. A crosspoint structure memory cell, by contrast, includes only a storage material member that stores memory data in a crosspoint between a bit line and a word line without using the selection transistor. With the configuration of this crosspoint structure memory cell, the data stored in the crosspoint between a selected bit line and a selected word line is directly read without using the selection transistor. The crosspoint structure memory cell has disadvantages such as a delay in operating rate caused by a parasitic current carried from unselected memory cells connected to the same bit line or word line as that to which the selected memory cell is connected and an increase in power consumption. However, attention has been paid to the crosspoint structure memory cell since this simple structure can ensure a large capacity. Further, there have been proposed semiconductor memory devices including crosspoint structure memory cells such as a magnetic RAM or MRAM (magnetoresistive random access memory), a FeRAM (ferroelectric random access memory), and a RRAM (resistance random access memory). The MRAM is a nonvolatile memory that stores data using a ferromagnetic tunneling magnetoresistance effect (tunneling magnetoresistance or TMR effect) exhibited by the storage material member of the memory cell, that is, using a resistance change due to difference in magnetization direction. The FeRAM is a nonvolatile memory that stores data using a ferroelectric property exhibited by the storage material member of the memory cell, that is, using a difference in residual polarization among electric fields. The RRAM is a nonvolatile memory that stores data using a colossal magnetoresistance effect (colossal magnetoresistance or CMR effect) exhibited by the storage material member of the memory cell, that is, using an effect of the resistance change among electric fields.
For instance, JP-A 2001-273757 discloses an MRAM including crosspoint structure memory cells in FIG. 2 and the like. JP-A 2003-288784 discloses a FeRAM including crosspoint structure memory cells in FIG. 2 and the like. JP-A 2003-68983 discloses an RRAM including crosspoint structure memory cells in FIG. 6 and the like.
A simplest conventional method for manufacturing the crosspoint structure semiconductor memory device will be described. FIG. 22 is a layout plan view that shows a configuration of a conventional memory cell having a crosspoint structure. In FIG. 22, reference symbol R1 denotes a region that defines a interconnecting pattern of lower electrode interconnectings B and reference symbol R2 denotes a region that defines a interconnecting pattern of upper electrode interconnectings T. It is noted that either the upper electrode interconnectings T or the lower electrode interconnectings B serve as word lines and that the other interconnectings serve as bit lines. FIGS. 23A, 23B, 24A, and 24B show the conventional manufacturing method in order of steps. FIGS. 23A and 24A are vertical cross-sectional views taken along line X-X′ of FIG. 22 and FIGS. 23B and 24B are vertical cross-sectional views taken along line Y-Y′ of FIG. 22.
First, an interlayer insulation film 27 under a memory cell is formed on a silicon semiconductor substrate 26. Next, a first electrode film 28 that becomes the lower electrode interconnectings B is deposited on an entire surface of the interlayer insulation film 27, and then etched by well-known photolithography using a resist patterned into a stripe as a mask. The lower electrode interconnecting pattern R1 is thereby formed as shown in FIGS. 23A and 23B.
A storage material member 29 that stores data is formed on the entire surface. Namely, if a FeRAM is to be manufactured, a material film that exhibits the ferroelectric property is formed. If an MRAM is to be manufactured, a material film that exhibits the ferromagnetic tunneling magnetoresistance effect is formed. If an RRAM is to be manufactured, a material film that exhibits the colossal magnetoresistance effect is formed.
Subsequently, a second electrode film 30 that becomes the upper electrode interconnectings T is deposited on the entire surface of the storage material member 29, and then etched by the well-known photolithography using a resist patterned into a stripe as a mask. The upper electrode interconnecting pattern R2 is thereby formed as shown in FIGS. 24A and 24B.
As described above, each crosspoint structure memory cell does not include a selection transistor, so that it is possible to highly integrate crosspoint structure memory cells. According to the conventional manufacturing method, with a view of realizing the high integration, each of the upper electrode interconnecting pattern and the lower electrode interconnecting pattern is formed into stripes (lines and spaces) periodically repeated according to a minimum processing dimension specified under a device rule of a manufacturing process normally used to manufacture the semiconductor memory device (a possible minimum line width and a possible minimum space under a manufacturing process restriction). In addition, the upper electrode interconnecting pattern and the lower electrode interconnecting pattern are arranged to be orthogonal to each other. It is noted that the minimum processing dimension is a dimension normally restricted by a photolithographic resolution.
In the crosspoint structure memory, a region (crosspoint) in which the upper electrode interconnecting and the lower electrode interconnecting cross each other is a part that functions as one memory cell. In the layout plan view of the memory cells formed by the conventional manufacturing method shown in FIG. 22, the crosspoints (memory cells) are repeatedly present each at a pitch 2F in an array in a lower electrode interconnecting direction and an upper electrode interconnecting direction, where “F” is the minimum processing dimension. An area of one memory cell is, therefore, 2F×2F=4F2 as indicated by a bold solid line region shown in FIG. 22. The conventional manufacturing method has, therefore, a disadvantage in that the memory cell area cannot be set smaller than 4F2 in theory.